1. Field of the Invention
The present invention relates to a method for fabricating a memory cell, and more particularly, to a nonvolatile memory cell.
2. Description of the Prior Art
Because a nonvolatile memory cell is rewritable and has qualities as fast transfer and low power consumption, it has been widely applied to portable products and become a critical device of many information, communication, and consuming electronic products. However, in order to provide light electronic products with high quality, it has become important for the current information industry and memory manufacturers to increase the device integration and quality of the nonvolatile memory cells.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of the structure of a memory cell 10 according to the prior art. The memory cell 10 is disposed on a substrate 12, and comprises a control gate 14 in a trench 26 on the substrate 12, a floating gate 16 disposed on the two sides of the control gate 14, at least a dielectric layer 18 placed between the control gate 14 and the floating gate 16, a cap layer 20 placed above the control gate 14, two word lines 22 and spacers 24 placed on the outer sides of the floating gate 16. The cap layer 20 comprises the function of protecting the control gate 14. According to the prior art, the thermal oxidation process is used to grow oxide materials on the top surface of the polysilicon control gate 14. However, due to the continuous increase of the device integration, the critical dimension (CD) of a single memory cell has to be continuously shrunk. Therefore, the difficulty of forming the sufficient thickness of the cap layer 20 on the top surface of the control gate 14, such as 600 angstroms (Å), increases dramatically according to the prior art method. Please refer to Table 1. Table 1 is the relationship table of the critical dimension of the trench 26 and the thickness of the cap layer 20.
TABLE 1Critical dimension of186014901350the trench (Å)Thickness of the cap676516435layer (Å)
Therefore, as indicated in Table 1, while the critical dimension of the memory cell 10 is getting smaller and smaller, the thickness of the cap layer 20 fabricated according to the prior art method is also getting thinner and thinner and becomes insufficient for protecting the control gate 14. This situation caused the difficulties in the fabrication or the unsatisfied quality of the memory cells 10, resulted in a bottleneck of the improvement of the integration of the nonvolatile memory cell.
In addition, while improving the device integration, the shrinking dimension of the control gate 14 will increase its resistivity. In order to solve the problem of resistivity, manufacturers considered using metal or other conductive materials to replace traditional polysilicon materials for fabricating the control gate 14. However, when metal materials are used to form the control gate 14, it is more difficult to form the required cap layer 20 on the control gate 14 through the traditional thermal oxidation process. As mentioned above, the industry needs to find other methods to replace the traditional thermal oxidation process to fabricate the cap layer 20 for ensuring the quality of the memory cell 10.